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PCI 9080
I2O Compatible PCI Bus Master I/O Accelerator Chip
Features
s PCI
Version 2.1 compliant Bus Master interface chip for adapters and embedded systems local bus supports nonmultiplexed 32-bit address/data, multiplexed 32- or 16-bit, and accesses of 32-, 16-, or 8-bit local bus devices
s Programmable
sI
2O compatible messaging unit s 3.3 or 5 volt PCI signaling, 5 volt core, low-power CMOS in 208-pin PQFP
s Two
independent programmable DMA channels for local bus memory to/from PCI host bus data transfers programmable FIFOs for zero wait state burst operation to/from local data transfers up to 133MB/sec bus runs asynchronously to the PCI bus 32-bit mailbox and two 32-bit doorbell registers Big Endian/Little Endian conversion compatibility with PCI 9060, 9060ES, 9060SD
s Eight
s PCI
s Local
Flexible Connection to the PCI Bus For add-in card and embedded system designers and integrators alike, the mission is clear: reduce the time to integrate new technology and time to market. Achieving this task requires the latest in I/O technology. PLX Technology, Inc. is committed to providing complete and proven PCI solutions with our PCI 9080 Bus Master I/O Accelerator interface chip. The PLX(R) PCI 9080 provides a compact, high performance PCI bus master interface with a programmable local bus. Integrating the latest in I/O technology, the PCI 9080 contains an Intelligent I/O (I2O) messaging unit in hardware that allows high performance and compatible software implementations of the I2O bus protocol specification. The highly flexible local bus solution can be configured to directly connect a wide variety of processors, controllers and memory subsystems. Combined with the PCI 9080RDK reference design kits, PCI SDK and I2O software development kits available from PLX, the design-in process is simple and painless with little or no glue logic. Customers are using the PCI 9080 with IBM PowerPC 40x, Motorola MPC850/860, Intel i960C/J/H, Hitachi Super H, MIPS R 3000/4000/5000, NEC V830/831, ARM, Motorola 68XXX, and others. Thoroughly tested and proven, PLX products have become the gold standard of the industry. Leading the way in PCI design, the PCI 9080 provides two intelligent DMA channels with scatter/gather, programmable burst modes, and asynchronous bus clocks to provide the best PCI throughput available. The versatility of the PCI 9080 also allows for a local processor to configure other PCI devices in the system. While the PCI 9080 is capable of keeping up with the most demanding of applications and the latest in technology, upward compatibility with existing PLX PCI I/O accelerators is maintained. The 9080 continues the PLX tradition of providing the highest performance and fully compatible PCI interface solutions.
s Eight
s Performs
s Upward
TECHNOLOGY
(R)
Technical Speci cations
Package PCI compliance I2O messaging unit Interface protocol PCI signaling Local bus speed Big/Little Endian conversion PCI Bus Speed PCI host capability Mailbox registers Doorbell registers Unaligned DMA transfer support Programmable local bus modes Mode C Mode J Mode S Serial EEPROM interface 208-pin PQFP PCI local bus specification, v. 2. 1 PCI extension of the Ispeci cation v.1.5 2O Direct bus master 3. 3v or 5v 0-40MHz Dynamic switching for direct slave, direct master, DMA, and the internal register accesses on the local side 33MHz max Type 0 or Type 1 PCI con guration cycles in direct master mode Eight 32-bit, accessed from PCI or local bus Two 32-bit, one from PCI to local bus, one from local bus to PCI bus From any byte boundary Selected through mode pins 32-bit address/32-bit data, non multiplexed 32-bit address/32-bit data, multiplexed 32-bit address/16-bit data, non multiplexed Supported
PCI 9080 Internal Block Diagram
Internal Registers PCI Con g Local Con g Run-Time DMA I2O Messaging PCI Bus State Machines
PCI Initiator (For Direct Master Xfers)
EEPROM Initialization
FIFOs
Dir. Master Write Dir. Master Read Dir. Slave Write Dir. Slave Read
DMA1 PCI/Loc DMA1 Loc/PCI DMA0 PCI/Loc DMA0 Loc/PCI
Local Bus State Machines
Local Slave (for Direct Master Xfers) Local Master (for Direct Master Xfers) Local Master (for Ch 1 DMA Xfers) Local Master (for Ch 0 DMA Xfers) Local Bus Interface
PCI Bus
PCI Bus Interface & Arbiter
PCI Initiator (For Ch 1 DMA Xfers) PCI Initiator (For Ch 0 DMA Xfers)
- Endian Conversion - Select Muxe or non-Muxe Addr/Data
Control Logic
I20 Messaging
DMA
DMA Chaining
Unaligned Xfer
TECHNOLOGY
(R)
Product Ordering Information
PCI 9080 I2O SDK PCI SDK PCI to Local Bus Master Chip I2O Software Development Kit for Motorola MPC860 CPU, Intel i960 CPU, IBM PPC 401 CPU PCI Software Development Kit for Motorola MPC860 CPU, Intel i960 CPU, IBM PPC 401 CPU
PLX Technology, Inc. 390 Potrero Ave. Sunnyvale, CA 94086 USA Tel: 1-800-759-3735 Fax: 1-408-774-2169 Email: info@plxtech.com Web Site: www.plxtech.com
*See PLX web site for latest version and product support information
(c) 1998 by PLX Technology, Inc. All rights reserved. PLX and PLXMon 98 are trademarks of PLX Technology, Inc. which may be regis tered in some jurisdictions. All other product names that appear in this material are for identi cation purposes only and are acknowledged to be trademarks or regist ered trademarks of their respective companies. Information supplied by PLX is believed to be accurate and reliable, but PLX Technology, Inc. assumes no responsibility for any errors that may appear in this material. PLX Technology reserves the right, without notice, to make changes in product design or speci cation.
9080-PB-010
9/98 5K
Local Bus
PCI Target (for Direct Slave Xfers)
- Select Bus Width 8,16 or 32 bit

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